The present invention generally relates to testing electronic circuits, and, more particularly, to re-use of test patterns for testing electronic circuits.
A system-on-chip (SoC) includes several standard interfaces that communicate with external hardware devices using standard communication protocols such as Universal Serial Bus (USB) interfaces, enhanced triple-speed Ethernet controller (ETSEC)/1588 interfaces, display interface unit (DIU) interfaces, synchronous serial interfaces (SSI), serial peripheral interfaces (SPI), and time-division multiplexing (TDM) interfaces. Since silicon is prone to defects, testing interfaces for accuracy of operation is of utmost importance before the SoC is shipped to customers. Testing involves several checks to ensure that the interfaces receive and transmit data to and from the external hardware devices accurately. An example of such tests is AC characterization (AC-Cz).
AC-Cz is performed to estimate input and output (I/O) specifications of a standard interface. The I/O specifications include measurements of input setup/hold values and output valid/hold values and must match with predetermined specifications for smooth and error free communication. A variation between the measurements and predetermined specifications indicates a fault in the circuitry implementing the standard interface.
Many times, identical standard interfaces installed in various SoCs, also known as re-use interfaces, require different sets of test patterns for testing. The differences may exist in power-on-reset (POR) configuration values, design bus architecture, design gaskets, design frequency of operation, pin-multiplexing arrangements, and pad activities of the SoCs. Since test patterns are cycle accurate, the above differences lead to repetition of the same test pattern generation activity across different SoCs at different time instances, making it imperative to generate different sets of test patterns for test re-use interfaces across different SoCs. For example, USB interfaces installed in Freescale Semiconductor™ P1022 and P1023 chips require different test patterns for AC-Cz. Architectural differences between SoCs also contribute to differences in test pattern activities for re-use interfaces.
Therefore, some test patterns for testing re-use interfaces must be regenerated. Regenerating test patterns is a cumbersome and laborious task that entails converting each interface activity into a tester format, stabilizing the tester formats across various process-voltage-temperature (PVT) corners, and defining new tester equations. Such efforts have a direct impact on the test costs and time-to-market.
Therefore, it would be advantageous to have a test system that eliminates the additional effort required for regenerating test patterns.